Aldec’s Active-HDL Verification Capabilities Enhanced to Support SystemVerilog Constructs and UVM

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Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has greatly enhanced the verification capabilities of LINK  ™, the company’s popular Windows-based Integrated Development Environment (IDE) for FPGA design creation and simulation.

These enhancements include the ability to compile and simulate SystemVerilog verification constructs, which in turn makes Active-HDL ideal for use in Universal Verification Methodology (UVM) test environments, and for functional coverage and constrained randomization simulations. In addition, a 64-bit simulation capability has been added by default to selected popular configurations, along with enhancements to Active-HDL’s block diagram and state machine editors.

“Aldec has supported UVM since version 1.0 was approved in 2011,” comments Louie De Luna, Director of Marketing. “We first supported the methodology with our high-end mixed HDL simulator Riviera-PRO, and we’re delighted that our Active-HDL IDE now also supports the latest UVM library as IEEE 1800.2-2017, as this makes life much easier for our users wishing to run third party Verification IP (VIP). Also, in addition to supporting native SystemVerilog verification constructs, VHDL packages can be compiled in such a way they can be used as SystemVerilog packages in the simulator.”

Active-HDL’s Installshield program has also been enhanced, and now supports 4k screens, plus the tool’s GUI has received a makeover; with menu changes, and new icons and dialog boxes.

First launched in 1997, Active-HDL is Aldec’s flagship IDE for FPGA design and verification. Today, the tool’s design flow manager can evoke more than 200 EDA and FPGA tools - during design entry, simulation, synthesis and implementation – and allows design teams to remain within a single environment during the entire FPGA development process. Active-HDL supports industry leading FPGA devices from Intel®, Lattice®, Microsemi™ (Microchip™), Quicklogic®, Xilinx® and more.

Active-HDL 11.1 is now available for LINK  .

About Active-HDL

Active-HDL™ is a Windows® based, integrated FPGA Design Creation and Simulation solution for team-based environments. Active-HDL’s Integrated Design Environment (IDE) includes a full HDL and graphical design tool suite and RTL/gate-level mixed-language simulator for rapid deployment and verification of FPGA designs.

About Aldec

Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. LINK 

Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are the property of their respective owners.

More news and information about Aldec, Inc.

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Business Wire: 19:00 GMT Tuesday 3rd December 2019

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